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1/17 may 2002 m68z128 5v, 1 mbit (128 kbit x 8) low power sram with output enable features summary n ultra low data retention current C10na(typical) C2.0a(max) n operation voltage: 5.0v 10% n 128 kbit x 8 very fast sram with output enable n equal cycle and access times: 55ns n low v cc data retention: 2.0v n tri-state common i/o n low active and standby power n automatic power-down when deselected n intended for use with st zeropower ? and timekeeper ? controllers figure 1. package tsop32 (n) 8 x 20mm
m68z128 2/17 table of contents description ....................................................................3 logicdiagram(figure2.).........................................................3 signalnames(table1.)..........................................................3 tsop connections (figure 3.) . . . ..................................................3 blockdiagram(figure4.).........................................................4 maximumrating.................................................................4 absolutemaximumratings(table2.) ...............................................4 dc and ac parameters. . ........................................................5 dc and ac measurement conditions (table 3.) . . . .....................................5 ac testing load circuit (figure 5.) ..................................................5 capacitance (table 4.) . . . ........................................................5 dccharacteristics(table5.) ......................................................6 operation......................................................................7 operating modes (table 6.) ........................................................7 readmode....................................................................7 addresscontrolled,readmodeacwaveforms(figure6.)..............................7 chip enable or output enable controlled, read mode ac waveforms (figure 7.). . ...........8 standby mode ac waveforms (figure 8.). . ...........................................8 readandstandbymodeaccharacteristics(table7.) .................................9 writemode..................................................................10 write enable controlled, write mode ac waveforms (figure 9.) .......................10 chipenablecontrolled,writemodeacwaveforms(figure10.)........................11 writemodeaccharacteristics(table8.) ..........................................12 low v cc dataretentionacwaveforms(figure11.)...................................13 low v cc dataretentioncharacteristics(table9.) ....................................13 partnumbering ...............................................................14 package mechanical information . . . ..........................................15 revisionhistory...............................................................16
3/17 m68z128 description the m68z128 is a 1 mbit (1,048,576 bit) cmos sram, organized as 131,072 words by 8 bits. the device features fully static operation requiring no external clocks or timing strobes, with equal ad- dress access and cycle times. it requires a single 5v 10% supply, and all inputs and outputs are ttl compatible. this device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. the m68z128 is available in tsop32 (8 x 20mm) package. figure 2. logic diagram table 1. signal names figure 3. tsop connections ai00647 17 a0-a16 w dq0-dq7 v cc m68z128 g e2 v ss 8 e1 a0-a16 address inputs dq0-dq7 data input/output e1 chip enable 1 e2 chip enable 2 g output enable w write enable v cc supply voltage v ss ground nc not connected internally a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 e2 a11 g e1 dq5 dq1 dq2 dq3 dq4 dq6 a15 w a16 a12 nc v cc a14 ai00657 m68z128 8 1 9 16 17 24 25 32 v ss
m68z128 4/17 figure 4. block diagram maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 and 120 seconds). 2. up to a maximum operating v cc of 5.5v only. 3. one output at a time, not to exceed 1 second duration. ai00665 row decoder a a (9) chip enable. input data ctrl dq dq (8) column decoder i/o circuits (8) a a chip enable. e1 w g chip enable memory array v cc v ss e2 symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg (1) storage temperature C65 to 150 c v io (2) input or output voltage C0.5 to v cc + 0.5 v v cc supply voltage C0.5 to 4.6 v i o (3) output current 20 ma p d power dissipation 1 w
5/17 m68z128 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. dc and ac measurement conditions note: output high z is defined as the point where data is no longer driven (see table 3, page 5). figure 5. ac testing load circuit table 4. capacitance note: 1. sampled only, not 100% tested. 2. outputs deselected. 3. at 25c. parameter m68z128 v cc supply voltage 4.5 to 5.5v ambient operating temperature 0 to 70c load capacitance (c l ) 100pf input rise and fall times 15ns input pulse voltages 0to3v input and output timing ref. voltages 1.5v ai00658b 5.0v out c l = 50pf or 5pf c l includes jig capacitance 1800 w device under test 990 w symbol parameter (1,2) min max unit c in input capacitance on all pins (except dq) 9 pf c out (3) output capacitance 9 pf
m68z128 6/17 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v (except where noted). 2. average ac current, outputs open, cycling at t avav minimum. 3. all other inputs at v il 0.8v or v ih 3 2.2v. 4. all other inputs at v il 0.3v or v ih 3 v cc C0.3v. symbol parameter test condition (1) min typ max unit i li input leakage current 0v vin v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 (2) supply current v cc = 5.5v; (C55) 30 70 ma i cc2 (3) supply current (standby) ttl v cc = 5.5v, e1 =v ih or e2=v il ,f=0 0.1 2 ma i cc3 (4) supply current (standby) cmos v cc = 5.5v, e1 3 v cc C 0.3v or e2 0.3v, f = 0 0.4 20 a v il input low voltage C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = C1ma 2.4 v
7/17 m68z128 operation the m68z128 has a chip enable power down fea- ture which invokes an automatic standby mode whenever either chip enable is de-asserted (e1 = high or e2 = low). an output enable (g )signal provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. operational modes are de- termined by device control inputs w ,e1 , and e2 as summarized in the operating modes table. table 6. operating modes note: x = v ih or v il . read mode the m68z128 is in the read mode whenever write enable (w ) is high with output enable (g ) low, and both chip enables (e1 and e2) are as- serted. this provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. valid data will be available at the eight output pins within t avqv after the last stable address, providing g is low, e1 is low and e2 is high. if chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t e1lqv , t e2hqv ,ort glqv ) rather than the address. data out may be indeterminate at t e1lqx ,t e2hqx and t glqx , but data lines will always be valid at t avqv . figure 6. address controlled, read mode ac waveforms note: e1 =low,e2=high,+g =low,w =high. operation e1 e2 w g dq0-dq7 power read v il v ih v ih v ih hi-z active read v il v ih v ih v il data output active write v il v ih v il x data input active deselect v ih x x x hi-z standby deselect x v il x x hi-z standby ai01078 tavav tavqv taxqx a0-a16 dq0-dq7 valid data valid
m68z128 8/17 figure 7. chip enable or output enable controlled, read mode ac waveforms note: write enable (w )=high. figure 8. standby mode ac waveforms ai00805 tavav tavqv taxqx te1lqv te1lqx te1hqz tglqv tglqx tghqz valid a0-a16 e1 g dq0-dq7 te2hqv te2hqx valid te2lqz e2 ai00806b tpd e2 i cc1 tpu i cc2 50% e1
9/17 m68z128 table 7. read and standby mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v (except where noted). 2. c l = 100pf. 3. c l = 5pf. 4. at any given temperature and voltage condition, t eihqz +t ezhqz is less than t eilqx and t ezlqx ,t ghqz is less than t glqx for any given device. symbol parameter (1) m68z128 unit C55 min max t avav read cycle time 55 ns t avqv (2) address valid to output valid 55 ns t e1lqv (2) chip enable 1 low to output valid 55 ns t e2lqv (2) chip enable 2 low to output valid 55 ns t glqv (2) output enable low to output valid 20 ns t e1lqx (4) chip enable 1 low to output transition 5 ns t e2lqx (4) chip enable 2 low to output transition 5 ns t glqx (4) output enable low to output transition 0 ns t e1hqz (3,4) chip enable 1 high to output hi-z 20 ns t e2hqz (3,4) chip enable 2 high to output hi-z 20 ns t ghqz (3,4) output enable high to output hi-z 20 ns t axqx (2) address transition to output transition 5 ns t pu chip enable low to power up 0 ns t pd chip enable high to power down 55 ns
m68z128 10/17 write mode the m68z128 is in the write mode whenever the w and e1 pins are low, with e2 high. either the chip enable inputs (e1 and e2) or the write en- able input (w ) must be de-asserted during ad- dress transitions for subsequent write cycles. write begins with the concurrence of both chip enables being active with w low. therefore, ad- dress setup time is referenced to write enable and both chip enables as t avwl ,t ave1l and t ave2h respectively, and is determined by the latter occurring edge. the write cycle can be terminated by the earlier rising edge of e1 ,w , or the falling edge of e2. if the output is enabled (e1 = low, e2 = high and g = low), then w will return the outputs to high im- pedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of op- eration. data input must be valid for t dvwh before the rising edge of write enable, or for t dve1h be- fore the rising edge of e1 or for t dve2l before the falling edge of e2, whichever occurs first, and re- main valid for t whdx ,t e1hdx or t e2ldx . figure 9. write enable controlled, write mode ac waveforms note: output enable (g )=low. ai00807 tavav twhax tdvwh data input a0-a16 e1 w dq0-dq7 valid e2 tavwh tave1l tave2h twlwh tavwl twlqz twhdx twhqx
11/17 m68z128 figure 10. chip enable controlled, write mode ac waveforms note: output enable (g )=high. if e1 goes high or e2 goes low simultaneously with w high, the output remains in a high-impedance state. ai00808 tavav te1hax tdve1h tdve2l a0-a16 e1 w dq0-dq7 valid e2 tave1h tave1l tavwl tave2l te1le1h te2lax tave2h te2he2l te1hdx te2ldx data input
m68z128 12/17 table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v (except where noted). 2. c l = 5pf 3. at any given temperature and voltage condition, t whqz is less than t wlqx for any given device. symbol parameter (1) m68z128 unit C55 min max t avav write cycle time 55 ns t avw l address valid to write enable low 0 ns t avwh address valid to write enable high 45 ns t av e1h address valid to chip enable 1 high 45 ns t ave 2l address valid to chip enable 2 low 45 ns t wlwh write enable pulse width 45 ns t whax write enable high to address transition 0 ns t whdx write enable high to input transition 0 ns t whqx (3) write enable high to output transition 5 ns t wlqz (2,3) write enable low to output hi-z 20 ns t ave 1l address valid to chip enable 1 low 0 ns t av e2h address valid to chip enable 2 high 0 ns t e1le1h chip enable 1 low to chip enable 1 high 45 ns t e2he2l chip enable 2 high to chip enable 2 low 45 ns t e1hax chip enable 1 high to address transition 0 ns t e2hax chip enable 2 low to address transition 0 ns t dvwh input valid to write enable high 25 ns t dve1h input valid to chip enable 1 high 25 ns t dve2h input valid to chip enable 2 low 25 ns
13/17 m68z128 figure 11. low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v (except where noted). 2. see figure 11 for measurement points. guaranteed but not tested. t avav is read cycle time. symbol parameter test condition (1) min typ max unit i ccdr supply current (data retention) v cc =3v,e1 3 v cc C 0.3v or e2 0.3v, f = 0 0.1 2 a v dr supply voltage (data retention) e1 3 v cc C 0.3v or e2 0.3v, f = 0 2v t cdr chip disable to power down e1 3 v cc C 0.3v or e2 0.3v, f = 0 0ns t er (2) operation recovery time t avav ns ai00659 data retention mode ter 5v tcdr v cc 3v v dr > 2.0v e1 2.2v e1 3 v dr C 0.3v e2 0.3v e2 0.8v
m68z128 14/17 part numbering table 10. ordering information example for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m68z 128 C55 n 1 tr device type m68z device function 128 = 1 mbit (128kb x 8) operating voltage blank = 4.5 to 5.5v speed C55 = 55ns package n = tsop32 (8 x 20mm) temperature range 1 = 0 to 70c shipping method for soic blank = tubes tr = tape & reel
15/17 m68z128 package mechanical information figure 12. tsop32 C 32-lead plastic thin small outline, 8 x 20 mm, package outline note: drawing is not to scale. table 11. tsop32 C 32-lead plastic thin small outline, 8 x 20 mm, package mechanical data symb mm inches min typ max min typ max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.950 1.050 0.0374 0.0413 b 0.150 0.270 0.0059 0.0106 c 0.100 0.210 0.0039 0.0083 d 19.800 20.200 0.7795 0.7953 d1 18.300 18.500 0.7205 0.7283 e 0.500 C C 0.0197 C C e 7.900 8.100 0.3110 0.3189 l 0.500 0.700 0.0197 0.0276 a 0 5 0 5 cp 0.100 0.0039 n32 32 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
m68z128 16/17 revision history table 12. document revision history date revision details may 1999 first issue 03/20/00 tsop32 package mechanical data changed (table 11) 09/21/00 i ccdr supply current changed (table 9) 04/03/01 reformatted; temp./voltage info. added to tables (table 4, 5, 7, 8, 9) 05/13/02 add reflow time and temperature footnote (table 2)
17/17 m68z128 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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